`include "define.v"
module REGFILE(
input wire clk,
input wire rst,
input wire [4:0] regaAddr,
input wire [4:0] regbAddr,
input wire regaRd,
input wire regbRd,
input wire we,
input wire [4:0] wAddr,
input wire [31:0] wData,
input wire hiRd,
input wire loRd,
input wire hiWr,
input wire loWr,
input wire [31:0] hiData,
input wire [31:0] loData,
output reg [31:0] regaData,
output reg [31:0] regbData
//output reg [31:0] out_reg 
);

reg [31:0] reg32 [31:0];
reg [31:0] hi;
reg [31:0] lo;
/*
integer i;
initial
begin
for(i=0;i<32;i=i+1)
begin
	reg32[i]=32'h0001;
end
end
*/
initial 
begin
reg32[0]=0;
reg32[31]=0;
end

always@(*)
if(rst==`Enable)       regaData=`Zero;
else if(hiRd==`Valid) regaData=hi;
else if(regaAddr==`Zero) regaData=`Zero;
else 				   regaData=reg32[regaAddr];

always@(*)
if(rst==`Enable)	   regbData=`Zero;
else if(loRd==`Valid) regbData=lo;
else if(regbAddr==`Zero) regbData=`Zero;
else 				   regbData=reg32[regbAddr];

always@(posedge clk)
begin
if(hiWr==`Valid) hi=hiData;
if(loWr==`Valid) lo=loData;
if(rst==`Disenable && we==`Valid && wAddr!=`Zero) reg32[wAddr]=wData;
else ;
end

//always@(posedge clk)  out_reg=reg32[1];

endmodule

